NASA Space
Instrument and Sensing Technology
Active Pixel Sensors
APS Chip
Image Sensors for Scientific, Commercial and Defense Applications
Close-up of APS Pixels
APS Chip
Close-up of APS Pixels
The CMOS active pixel sensor (APS) is a second generation solid state sensor technology that was invented and developed at JPL. The goal of the advanced imager technology effort at JPL has been the development of a "camera on a chip," which would have a full digital interface. Only digital power signals and power are input to the chip and only digital data is transmitted off chip. Miniaturization and simplification of the sensor electronics has high leverage for reducing system mass, volume and power. To achieve smaller and simpler sensor electronics will require the imaging instruments be highly integrated. By using CMOS APS technology low power, low volume, highly integrated imaging systems can now be realized. A complete imaging system would only require optics, a power supply, a CMOS APS imaging array with on-chip ADC and a microprocessor to upload the instructions to the imager and download the image data.
CMOS APS technology utilizes active transistors in each pixel to buffer the photo-signal. The performance of this technology is comparable to charge-coupled devices (CCDs). The CMOS APS approach does have several important advantages over CCDs. Since the CMOS APS is inherently CMOS compatible, it is easy to integrate on-chip timing, control and drive electronics, reducing system cost and complexity. The cost of fabricating a CMOS wafer is one-third the cost of fabricating a similar wafer using a specialized CCD process. Other advantages of the CMOS APS are: TTL-compatible operation (0-5V), only a single power supply is required, electronic shuttering, readout windowing, variable integration time and pixels in the array can be addressed randomly. APS technology can be implemented using widely available techniques to obtain enhanced UV/blue response. It is also possible to implement this technology using a commercially available radiation hard CMOS process, which would be of interest for space-borne instruments. For applications where low power dissipation is crucial, APS arrays have been successfully operated at 3 V.
NASA applications for CMOS APS technology include low power imagers for micro-spacecraft, optical communications, star trackers and machine vision for space micro-rovers. Examples of commercial applications include biomedical imaging, multimedia machine vision, high speed imaging and low cost video phones. This technology has been successfully transferred to several commercial companies. This technology has been proposed to be used for several scientific missions.
Research sponsored by the NASA Office of Space Access and Technology of highly integrated imaging systems for miniaturized deep space instruments has led to the development of several commercial applications of this technology. It is apparent that the CMOS APS approach has high potential to open new markets for low cost, non-camcorder consumer imaging systems.
Contact: Dr. Bedabrata Pain, (818) 354-8765
bedabrata.pain@jpl.nasa.govOriginally written September 1, 1994 by Dr. Eric Fossum (now at Photobit Corporation). Out-of-date information updated in March and May 1995 by Gordon Johnston. Corrections since then have been mostly link updates, etc.
Created: September 30, 1994. Last update: September 18, 1997. Please see Gordon Johnston's Disclaimer and Web Policy page. Tools used include Doctor HTML and WebTechs HTML Validation Service. Originally created by Gordon Johnston. Due to changing position assignments, this page will now be maintained by Glenn Mucklow.
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