Algorithmically Specialized Parallel Architecture for Robotics

NASA s Jet Propulsion Laboratory, Pasadena, California

A computing system called the Robot Mathematics Processor (RMP) contains a large number of processor elements (PEUs) connected in various parallel and serial combinations that are reconfigurable via software. The RMP is a special purpose architecture designed for solving diverse computational problems in robot control, simulation, trajectory generation, workspace analysis, and the lik e. It is an algorithmically specialized parallel architecture capable of exploiting the common properties of the parallel algorithms developed for this class of problems. It can exploit parallelism in different forms and at several computational levels in these computation-intensive applications. From the perspective of interaction with other computing equipment, the system can be regarded as a processor that can be attached to the bus of the external host as a part of bus memory. The system interacts with the external host processor(s) controlled by the user(s). The external host processor can be any stand-alone computer or a bus-oriented multiprocessor system. The data and instructions from the external host to the RMP and the results from the RMP to the external host are communicated through a dual-access shared memory that is part of the bus memory. The RMP is activated by a procedure call from the external host, which is executed via a "write" operation in a designated address and is interpreted as an Rinterrupt" by the RMP. This memory mapping scheme provides maximum flexibility and speed inasmuch as the data-transfer rate is limited by the read/write cycle of the external host. A bus adapter provides the required interface for different buses. The system (see figure) contains a general-purpose processor, which is called the internal host, and n single-instruction multiple-data (SIMD) parallel processors, which are called "cells." The host processor is the control unit of t he system: it handles the interface with the external host, controls the activities of the cells, and performs the required input/output operations. It also handles the serial and data dependent computation. The ensemble of cells performs parallel computation. By using two synchronization mechanisms, the ensemble can perform parallel computation in different combinations of multiple-instruction multiple-data (MIMD) and SIMD modes. The first mechanism is a global clock- based one similar to systolic arrays. The cells are driven by a common clock that allows the ensemble to perform parallel computation in a two-level SIMD/SIMD mode. The second mechanism is a local data-driven one similar to wave front arrays that allows each cell to operate asynchronously and the ensemble to perform parallel computation in a two-level MIMD/SIMD mode. The major advantage of the system lies in the design of the cells, which provides flexibility and reconfigurability superior to those of previous SIMD processors.

Each cell contains six processor elements (PE's), which are simple floating-point processors capable of performing such primitive operations as multiplication, addition, and the like. Each PE has a three-bus architecture with an internal dat a path that enables such accumulative operations as sum-of product and Newton- Raphson iterations for performing division. Two table lookup units (TLU's) provid e the seed values for initiating the division operations by Newton-Raphson method.

They are also used for trigonometric-functions evaluation. Basically, the PE's are organized in two groups, each containing three PE's. In solving problems for robot control and simulation, the two groups can perform, two basic (matrix-vector) operations in parallel, while each group can exploit parallelism in the operation. Also, each group can be considered as an independent SIMD subsystem or a pipeline stage, making it possible to decompose the whole system into two independent MIMD/SIMD parallel architectures or two n-stage pipes. The cell control mechanism is designed to provide such flexibility and reconfigurability while also minimizing the instruction length and complexity. Each cell has three control units: one master control unit (or microcontroller) and two slave control units (or nanocontrollers). The master control unit controls the overall activities of the cell and provides the instruc tions to be executed by all the PE's. Each slave control unit performs the read-write operations for one group of PE's. The slave control units are run by a clock twice faster than that of the master control unit. This allows a complete overlapping of the read/write and arithmetic operations. In addition, data can be fed to the PE's with adequate speed while also reducing the memory architecture complexity The direct path among the PE's of each group enables a linear interconnection among them. A multiplexer is used to provide other topologies among the PE's of each cell. Under the control of the master control unit, the multiplexer can establish a ring topology for each group, or a ring topology among all PE's of th e cell, or a linear topology among all PE's of the cell. The latter case is used to transform the whole system into a uniform "pipe.''

Point of Contact:
Amir Fijany
Mail Stop 525-3660
Jet Propulsion Laboratory
4800 Oak Grove Drive
Pasadena CA 91109
818-306-6491
fijany@telerobotics.jpl.nasa.gov

Antal K. Bejczy
Mail Stop 198-219
Jet Propulsion Laboratory
4800 Oak Grove Drive
Pasadena CA 91109
818-354-4568
bejczy@telerobotics.jpl.nasa.gov

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Last updated: May 10, 1996